The present invention relates, in general to the design and testing of integrated circuits and, more specifically, to a method and a program product for designing circuits in a manner to facilitate quiescent current (IDDq) testing of the circuit and to a circuit designed according to the method.
The complexity of semiconductor circuits often requires partitioning the circuit design into several core modules or blocks, generally referred to as design hierarchy. The blocks can be verified and laid out independently from each other. This design approach has been used for a long time and has several benefits, the most significant of which are to accelerate the development of the design by allowing several designers to work in parallel and to reduce the difficulty for design automation tools by avoiding the need to manipulate the description of the entire circuit at once.
It has been shown recently that scan test methods can be adapted to a hierarchical design methodology by adding scannable memory elements around the periphery of core modules or by modifying functional memory elements near the periphery of modules and providing an internal and external mode of operation to these memory elements (see, for example, “A structured and Scalable Mechanism for Test Access to Embedded Reusable Cores”, ITC '98. paper 12.1, Marinessen et al. and Applicants' co-pending U.S. patent application Ser. No. 09/626,877 filed on Jul. 27, 2000 for “Hierarchical Design and Test Method and System, Program Product Embodying the Method and Integrated Circuit Produced Thereby”, both incorporated herein by reference.) In this divide-and-conquer approach, scan tests of modules can be prepared in advance by the designer of the core module or block without any knowledge of the context within which it will be used.
The preparation of the scan tests involves at least the verification of design-for-test rules and calculation of test coverage. During the internal scan test of blocks, the state of memory elements outside of the modules is irrelevant. The preparation also involves the generation of a simplified model of the module that can be used to perform the same steps at the next level of hierarchy of the design. The use of the simplified model eliminates the need to manipulate the entire description of core modules. During the external scan test of modules, the state of memory elements that are not involved (i.e. not near the periphery of the module) is, again, irrelevant. Core modules can be tested in parallel or sequentially.
There is one type of test that does not readily lend itself to this hierarchical design methodology. During circuit manufacturing, it is often required to measure the quiescent current (IDDq) for different states of the circuit. The quiescent current is used as a complement to the scan tests described earlier. The state of the circuit is defined by the values loaded in the memory elements of the circuit. The designer needs to ensure that each state of the circuit corresponds to a state where no static current is consumed in a good circuit. A software tool (rules checker) is typically used to perform this task. The designer can also calculate the fault coverage of the faults covered by this test using a fault simulator and/or an automatic test pattern generator (ATPG). To date, the quiescent current test, and the analysis required to perform it, requires considering the entire circuit at once which is becoming virtually impractical for large circuits.
Applicant's above mentioned cross-reference application describes and claims a circuit design and test method and circuit in which hierarchical blocks are have been designed so that they either do not include any circuit states which cause elevated current levels or which contain very few such states. Such circuits not only allow the use of pseudo-random test patterns, but also allow the use of scan chains with branches. Applicant's prior invention describes a method of excluding test patterns which cause elevated IDDq states. There exists some circuits, however, which require block specific test patterns and, therefore, the non-specific, pseudo-random test patterns cannot be employed. The present invention provides a circuit and method for designing such circuits to facilitate quiescent current testing thereof.